The fabrication of semiconductor circuits generally repeatedly performs a series of processes including lithography, deposition, etching, and the like to form layer-stacked integrated circuits. However, as the feature size of the semiconductor device reduces, the complexity of conventional methods, and the parameters of etching processes for various materials become more and more difficult to control, such that the breakdown rate increases due to inappropriate control of etching rate or voltage.
Conventional methods for forming memory devices generally include patterning a gate conductor, wherein a mask layer is removed, and then a spacer is formed to define the gate conductor. However, because the spacer having a curved shape causes the etching process more difficult to control, the edge of the gate conductor may be damaged during the process of removing the spacer.
Therefore, it is desired to provide a method for forming a semiconductor structure, which reduces the required steps and avoids the edge damage of the gate conductor clarity patterning the gate conductor, and defines floating gates of the memory device by using a self-aligned manner.